1. Field of the Invention
The present invention relates to an integrating analog to digital converter (ADC), and more particularly, to an integrating ADC in which the residual integrator voltage at the end of "runup" is determined using a conventional ADC in lieu of "rundown".
2. Description of the Prior Art
Integrating ADCs having up to 8 1/2 digit (28-bit) resolution and 7 1/2 digit (25-bit) integral linearity are known.. Integrating ADCs have been used in the prior art because of their ability to make high-resolution measurements; however, integrating ADCs have previously been relatively slow. Numerous attempts have been made to increase the speed of such integrating ADCs without adversely affecting the resolution of the output. However, such efforts have met with limited success since the speed of the integrating ADC is generally inversely proportional to the resolution of the output. In other words, in integrating ADCs, speed has generally been traded off for resolution.
Such ADCs of the prior art now will be described in detail with reference to FIGS. 1-8.
FIG. 1 illustrates a prior art dual-slope type integrating ADC, while FIG. 2 shows a waveform diagram illustrating the principle of operation of the circuit of FIG. 1. A dual-slope type integrating ADC of the type shown operates by first shorting the integrator capacitor C by closing switch SW3 so that the integrator is at zero volts. Then, at time t.sub.0, an unknown input voltage (the voltage to be measured), V.sub.in, is applied to resistor R by closing switch SW1 for a fixed length of time t.sub.u. The unknown input voltage V.sub.in is then integrated for the duration t.sub.u, a period of time which is generally known as "runup". At the end of runup (i.e., when switch SW1 is opened), the output of the integrator, V.sub.0, can be shown to be: ##EQU1## When V.sub.in is time invariant, Equation (1) reduces to: ##EQU2##
At the end of runup, a known reference voltage, V.sub.ref, with a polarity opposite to that of V.sub.in is connected to the same resistor R by closing switch SW2. A counter is started at this time and is stopped when the output of the integrator crosses through zero volts as shown in FIG. 2. This period of capacitor discharge is generally known as "rundown". The counter contents at the time the integrator crosses through zero volts can be shown to be proportional to the unknown input V.sub.in as: ##EQU3## where t.sub.d is the time required to complete rundown (i.e. t.sub.4 =t.sub.2 - t.sub.u in FIG. 2). Then, by substituting Equation (2) into Equation (3) and solving for V.sub.in : ##EQU4## Finally, if N.sub.u is defined as the number of clock periods T.sub.ck during runup and N.sub.d is defined as the number of clock periods during rundown, time cancels from Equation (4) so that: ##EQU5##
Thus, in accordance with the prior art dual-slope type integrating ADC technique, the output is insensitive to the value of most of the circuit parameters because the values of R, C, and T.sub.ck all cancel from Equation (5). Moreover, in accordance with the prior art dual-slope type integrating ADC technique a single circuit can be designed to trade speed for resolution so that if the runup time is shortened the resolution will be reduced, as will the time required to make the measurement.
However, the prior art dual-slope type integrating ADC technique is disadvantageous in that the resolution and the speed are limited. In particular, the time T.sub.m required for a dual-slope type integrating ADC to make a measurement is determined by: EQU T.sub.m =2T.sub.ck M, (6)
where T.sub.m is the minimum theoretical time to make a full-scale measurement, T.sub.ck is the period of the ADC clock, and M is the number of counts of resolution in the full-scale measurement. Thus, as is apparent from Equation (6), for a clock frequency of 20 MHz measuring a signal with a resolution of 10,000 counts requires at least 1 millisecond. In addition, the resolution of the dual-slope type integrating ADC is limited by the wide band circuit noise and the maximum voltage swing of the integrator, for the wideband circuit noise has been found to limit how precisely the zero crossing can be determined. Since determining the zero crossing to an accuracy of greater than a millivolt is very difficult, the dual-slope technique generally only can provide four or five digits of resolution. For example, if the maximum voltage swing of the integrator is 10V and the accuracy is .+-.1mV, the resolution is 10V/1 mV=10,000 counts, which is approximately 4 to 5 digits of resolution (i.e., 13 bits or 2.sup.13 counts).
The speed of the dual-slope type integrating ADC shown in FIG. 1 has been nearly doubled by using a pair of resistors, one for runup and the other for rundown, as shown in FIG. 3. In the ADC circuit of FIG. 3, the unknown voltage V.sub.in is connected through switch SW1 to resistor R.sub.u. Similarly, reference voltage V.sub.ref is connected through switch SW2 to resistor R.sub.d, which is much greater than the resistor R.sub.u used during runup. As a result, the runup time is shortened by the ratio of the two resistors while the same resolution is maintained during rundown, as shown in FIG. 4. The cost of the added speed is an additional resistor and a sensitivity to the ratio of the two resistors. In other words: ##EQU6## The time required for runup can be correspondingly reduced.
Another prior art integrating type ADC is shown in FIG. 5. FIG. 5 shows an integrating type ADC which utilizes multislope rundown to reduce the time to perform rundown. In other words, instead of using a single resistor for rundown (i.e., a single slope) as in the prior art embodiments of FIGS. 1-4, the multislope rundown circuit uses several resistors (i.e., multiple slopes) and seeks zero several times, each time more precisely as shown in FIG. 6. The ratio of one slope to another is the power of some number base, which for purposes of description is base 10.
As shown, four slopes are used having weights of 1000, 100, 10 and 1, and each slope is given a name denoting its weight and polarity. For example, -R.sub.b is a positive slope with 1000 counts per clock period while R.sub.b /10 is a negative slope with 100 counts per clock period. A slope is considered to be positive if it transfers charge to the integrator, and since the integrator is an inverting circuit, it moves in a negative direction during a positive slope and vice-versa.
Runup occurs across resistor R.sub.a when switch SW3 is closed in the same manner as in either FIG. 1 or FIG. 3. However, multislope rundown begins at time t.sub.u by switching on the steepest slope, -R.sub.b, by closing switch SW5 and opening switch SW3. This slope remains on until the integrator output crosses zero as shown in FIG. 6, at which time SW5 is opened and the next slope, +Rb/10, is turned on by closing switch SW2 until the output V.sub.o crosses back through zero. The slope -Rb/100 follows next by closing switch SW4, and when the output V.sub.o crosses back through zero, switch SW1 is then closed so that slope +Rb/1000 follows. Each slope thus determines the integrator's zero crossing ten times more precisely than the previous slope. In other words, each slope adds another digit of resolution to the rundown.
In the prior art embodiment of FIG. 5, if each slope is turned off within one clock period of crossing zero, each subsequent slope would require ten or fewer clock periods to cross zero. Thus, the theoretical time t.sub.4 to complete a multislope rundown is: EQU t.sub.d &lt;NBT.sub.ck, (8)
where N is the number of slopes and B is the number base of the slope ratios. However, in practice the necessary time to complete rundown is higher because it is not always possible to turn off each slope within a clock period of its zero crossing. Delays in detecting the zero crossing and delays in responding by turning off the slopes cause the actual time for multislope rundown to be: EQU r.sub.d &lt;kNBT.sub.ck, (9)
where k is a factor greater than one. Thus, any delay in turning off a slope results in the integrator's output overshooting zero. As a result, for each clock period of overshoot, the following slope must take B clock periods to overcome the overshoot. Nevertheless, the multislope rundown technique shown in FIGS. 5 and 6 has resulted in an ADC which is 125 times faster than the equivalent dual-slope type integrating ADC of the type shown in FIGS. 1-4.
This multislope rundown technique has been optimized for even faster measurements by choosing the optimum base. In other words, by writing the number of slopes N as log.sub.B (M), where M is the number of counts of resolution required from rundown, then EQU t.sub.d &lt;kBlog.sub.B (M)T.sub.ck. (10)
From Equation (10) it can be seen that base e is the optimum base for any required resolution. In fact, using base e in Equation (10) results in a rundown time which is 60% faster than the rundown time for a base of 10.
However, despite the significant improvement in speed, multislope rundown is more expensive to implement since a resistor network having several precision resistors and precise ratios must be provided. In particular, the tightest ratio tolerance is the reciprocal of the weight of the steepest slope and must be maintained to ensure linear ADC operation. Moreover, multislope rundown requires a more complex control circuit to control and accumulate the measurement. It is thus desirable to develop a rundown technique which can be implemented less expensively without sacrificing speed or simplicity.
On the other hand, the resolution of the ADC conversion also has been improved by modifying the runup technique. For example, multislope runup may be used for increasing the resolution of the ADC. Multislope runup is a modification of dual-slope runup whereby the ADC is allowed to have an effective voltage swing much larger than the physical limitations of the integrator circuit hardware. This technique involves periodically adding and subtracting a reference charge to or from the integrator input during runup such that the charge from the unknown input V.sub.in plus the reference charge V.sub.ref is never large enough to saturate the integrator. By accounting for the total amount of reference charge transferred to the integrator during runup and adding this number to the result of rundown, the resulting measurement can have much higher resolution. A circuit for implementing multislope runup is shown by way of example in FIG. 7.
As shown in FIG. 7, a precise amount of reference charge is generated by applying either a positive reference voltage +V.sub.ref to resistor R.sub.a via switch SW.sub.a or a negative reference voltage -V.sub.ref to resistor R.sub.b via switch SW.sub.b for a fixed amount of time. As a result, like multislope rundown, the positive voltage V.sub.ref adds charge to the integrator while the negative voltage -V.sub.ref subtracts charge from the integrator. If the circuit is designed such that currents across resistors R.sub.a and R.sub.b have equal magnitudes that are slightly greater than that of the current generated by a full-scale input signal, then the reference currents will always be able to remove the charge accumulating as a result of the input signal. Therefore, the integrator can be kept from being saturated by periodically sensing the polarity of the integrator output using a comparator, for example, and appropriately closing either switch SW.sub.a or SW.sub.b such that the integrator output is forced to move towards or across zero.
FIG. 8 shows a typical multislope runup waveform where the dashed line shows the effective voltage swing (without reference charge being put into the integrator). As can be seen from FIG. 8, the integrator output stays within the limits of the circuit while the effective voltage swing ramps far beyond the limit. Such a multislope runup technique thus has two distinct advantages over a dual-slope runup as shown in FIGS. 1-6. Namely, (1) the runup can be continued through any length of time without saturating the integrator, and (2) increased resolution can be achieved during runup as well as during rundown.
Although the multislope runup technique allows for improved resolution, when used with multislope rundown the resulting time period for a reading may be quite great for a high resolution output. For example, about 150 microseconds are required to perform multislope rundown alone for a resolution of about 6 digits. Moreover, dedicated high speed logic must be used for this purpose as well as custom integrated circuitry which is quite expensive. It is thus desirable to shorten the time period for rundown so that speed can be improved and to make the ADC more cost effective without sacrificing resolution and linearity. The present invention achieves these goals.